1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to an efficient method of soft error recovery within a flip-flop.
2. Description of the Relevant Art
Modern microprocessors may include one or more processor cores, or processors, wherein each processor is capable of executing instructions of a software application. Modern processors are typically pipelined, wherein the processors include one or more data processing stages connected in series with storage elements placed between the stages. The storage elements typically are flip-flop circuits. The output of one stage is made the input of the next stage during each transition of a clock signal.
Some processors may have multiple pipelines. Therefore, the number of flip-flop circuits, which has reached the hundreds of thousands on modern designs, has been increasing with each generation of processors. Further, the geometric dimensions of devices and metal routes on each generation of processors is decreasing. This geometric decrease causes a decrease in the capacitance used for storage of charge on nodes of the semiconductor chip, although the cross-capacitance of metal routes increase. Also as the channel lengths of transistors decrease, electrostatic fields at the source and drain terminals of transistors increase, which increases both the hot-electron effects and the potential failure.
In order to both reduce the power consumption of the chip, which is proportional to the square of the power supply voltage, and reduce the electrostatic fields within the transistors, the power supply voltage is decreased as well. There is a limit to the power supply voltage reduction, since this reduction deceases the amount of current that may flow through a transistor and, thus, increases the propagation delays through transistors. If the threshold voltages are reduced in order to turn-on the transistors sooner and aid in maintaining performance, then transistor leakage current increases. An increase in transistor leakage current both increases power consumption and the potential for logic failure.
With both the node capacitance and the supply voltage decreasing over time with the next generations of new processors, the amount of electrical charge stored on a node decreases. Due to this fact, nodes used for storage are more susceptible to radiation induced soft errors caused by high energy particles such as cosmic rays, alpha particles, and neutrons. This radiation creates minority carriers at the source and drain regions of transistors to be transported by the source and drain diodes. The change in charge compared to the total charge, which is decreasing with each generation, stored on a node may be a large enough percentage that it surpasses the circuit's noise margin and alters the stored state of the node. Although the circuit is not permanently damaged by this radiation, a logic failure may occur.
For the above reason, memories such as static random access memory (SRAM) use error correcting code (ECC) to detect and correct soft errors. Sequential elements, such as flip-flops, may use larger capacitance nodes or redundant latches within their design in order to combat soft errors. However, these techniques significantly increase the area and propagation delay of the flip-flop.
In view of the above, an efficient method for detecting and correcting soft errors in a flip-flop circuit is desired.